Assembly Language
Copyright Brian Brown, 1988-2000. All rights reserved.
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68000 Addressing Modes


MOVE.length(B, W, L) EAsource, EAdestination

Note that the first operand is the source, and the second operand is the destination.


Address/Data Register Direct
These addressing modes specify the operand as one of sixteen general purpose registers or one of six control registers (SR, VBR, SFC, DFC, CACR, CAAR).


Address Register Indirect
This addressing mode specifies the operand in memory, the address of which is specified by one of the address registers.

The operand is found in the address specified by an address register.


	EA = (An)

	Assembler Syntax: (An)

address register indirect


	* asm001.asm
	*
	* shows address register indirect
	ORG $50
	JMP BEGIN

	ORG $60  * data segment
	DSEG EQU $60
	DC.W $FEDC

	ORG $70  * code segment
	BEGIN: MOVE.W  #DSEG,A0 * point A0 to location $0050
	MOVE.W  (A0),D0 * load D0 from (A0), eg $0050

	LP1: JMP LP1


ADDRESS REGISTER INDIRECT WITH POSTINCREMENT
This addressing mode specifies the operand in memory, the address of which is specified by one of the address registers. After the operand is used, the value in the address register is incremented according to the size of the operand.


	  +1	 byte
	  +2	 word
	  +4	 long word

The operand is found in the address specified by an address register.


	EA = (An)
	An = An + SIZE
	Assembler Syntax: (An)+

address register indirect postinc


	* ref asm002.asm
	*
	* shows address register indirect with post increment
	ORG     $50
	JMP BEGIN
 
	ORG $60  * data segment
	DSEG EQU $60
	DC.W $FEDC
	DC.W $BA98

	ORG $70  * code segment
	BEGIN: MOVE.W  #DSEG,A0 * point A0 to location $0060
	MOVE.W  (A0)+,D0 * load D0 from (A0), eg $0060
	MOVE.W  (A0)+,D1
	LP1: JMP     LP1


ADDRESS REGISTER INDIRECT WITH PREDECREMENT
This addressing mode specifies the operand in memory, the address of which is specified by one of the address registers. Before the operand is used, the value in the address register is decremented according to the size of the operand.


	  -1	 byte
	  -2	 word
	  -4	 long word

The operand is found in the address specified by an address register.


	EA = (An)
	An = An + SIZE
	Assembler Syntax: -(An)

address register indirect with predec


	* asm003.asm
	*
	* shows address register indirect with pre decrement
	ORG     $50
	JMP BEGIN
 
	ORG $60   * data segment
	DSEG EQU $60
	DC.W $FEDC
	DC.W $BA98

	ORG $70    * code segment
	BEGIN: MOVE.W  #DSEG+4,A0 * point A0 to location $0064
	MOVE.W  -(A0),D0  * load D0 from (A0), eg $0062
	MOVE.W  -(A0),D1
	LP1: JMP     LP1


ADDRESS REGISTER INDIRECT WITH DISPLACEMENT
This addressing mode specifies the operand in memory, the address of which is specified by one of the address registers plus the sign extended 16 bit displacement specified as part of the instruction.


	EA = (An) + d16
	Assembler Syntax: (d16, An)

address register indirect plus disp


	* asm004.asm
	*
	* shows address register indirect with displacement
	ORG     $50
	CSEG EQU $50
	JMP BEGIN
 
	ORG $60  * data segment
	DSEG EQU $60
	DC.W $FEDC
	DC.W $BA98

	ORG $70  * code segment
	BEGIN: MOVE.W  #CSEG,A0 * point A0 to location  $0050
	MOVE.W  $10(A0),D0 * load D0 from (A0), eg $0060
	LP1: JMP     LP1

Note the different syntax required for this instruction.


ADDRESS REGISTER INDIRECT WITH INDEX (8-BIT)
This addressing mode specifies the operand in memory, the address of which is specified by one of the address registers plus the value in an index register, plus the sign extended 8 bit displacement specified as part of the instruction.


	EA = (An) + (Xn) + d8
	Assembler Syntax: (d8, An, Xn.SIZE)

address register indirect plus index


	* asm005.asm
	* shows address register indirect with index plus displacement
	* 

	ORG     $50
	CSEG EQU $50
	JMP BEGIN
 
	ORG $60  * data segment
	DSEG EQU $60
	DC.W $FEDC
	DC.W $BA98

	ORG $70  * code segment
	BEGIN: MOVE.W  #CSEG,A0 * point A0 to location  $0050
	MOVE.W  #$0E,A1 * load A1 as index register
	MOVE.W $02(A0,A1.W),D0
	LP1: JMP     LP1  

NOTE the different syntax required for this assembler!!!!


ABSOLUTE ADDRESSING MODES
The address of the operand is specified in the extension word(s) as part of the instruction.


IMMEDIATE DATA
This addressing mode specifies the address of the operand in memory, the address follows the opcode. The address is specified high order byte first. The immediate data size is either Byte, Word or Long.


	EA = given
	Assembler Syntax: #xxx.SIZE

	* asm008.asm
	*
	* shows immediate addressing
	*
	CR   EQU $0A
	LF   EQU $0D
	PPI_INIT  EQU $7f03
	PPI_CTRL_ADR  EQU $07fffffff
	PPI_DATA_ADR EQU $07ffffffe
	ORG  $50
	CSEG EQU  $50
	MOVE.W #PPI_INIT,D0  * move PPI init bytes to D0
	MOVE.L #PPI_CTRL_ADR,A0 * move PPI control reg to A0
	MOVE.L #PPI_DATA_ADR,A1 * move PPI data reg to A1
	MOVE.B D0,PPI_CTRL_ADR * initialise PPI
	ROR  #8,D0
	MOVE.B D0,PPI_CTRL_ADR
	MOVE.B #CR,D0
	MOVE.B D0,(A1)  * CR to PPI data reg
	LP1: JMP  LP1


PROGRAM COUNTER WITH DISPLACEMENT
This addressing mode permits memory to be accessed relative to the current value of the Program Counter. The major use is for jumps in position independant code, and reading constants in code segments.


	EA = (PC) + d16
	Assembler Syntax: (d16, PC)


	* asm009.asm
	*
	* shows pc indirect with displacement
	*
	ORG $50
	CSEG EQU $50
	MOVE TABLE,D0 * moves TABLE[0] into D0
	LP1: JMP LP1

	TABLE:
	DC.W 20
	DC.W 32
	DC.W 64


PROGRAM COUNTER WITH INDEX
This addressing mode extends the program counter relative mode to include an index and offset value. The effective address of the operand is the sum of the extension word, a sign extended 8-bit displacement integer, and the contents of an index register. This effectively handles lists or tables.


	EA = (PC) + (Xn) + d8
	Assembler Syntax: (d8, PC, Xn)

	* asm010.asm
	*
	* shows pc indirect with index
	*
	ORG $50
	CSEG EQU $50
	JMP START

	TABLE: 
	DC.B 20
	DC.B 32
	DC.B 64

	START:
	MOVE #0,A0   * use A0 as index register
	MOVE.B TABLE(A0),D0 * moves TABLE[0] into D0
	ADD #1,A0
	MOVE.B TABLE(A0),D1 * moves TABLE[1] into D1
	LP1:    JMP     LP1
	END


IMPLICIT REFERENCE


	SR = Status Register (16bit)
	CCR = Condition Code Register (8bit)
	 to CCR
	  ANDI
	  EORI
	  MOVE
	  ORI

	to SR
	  ANDI
	  EORI
	  MOVE
	  ORI

	from SR
	  MOVE


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Copyright Brian Brown, 1991-2000. All rights reserved.