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Hardware Fundamentals
Copyright Brian Brown, 1992-2000. All rights reserved.
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CPU AND MEMORY
The objective of this section is to

At the end of this section, you should be able to


TopThe Computer System
The functional diagram of a typical computer system is shown below,

Computer system
Fig 4_1: Computer System Block Diagram

The address bus is used by the processor to select a specific memory location within the memory subsystem, or a specific peripheral chip.

The data bus is used to transfer data between the processor and memory subsystem or peripheral devices.

The control bus provides timing signals to synchronise the flow of data between the processor and memory subsystem or peripheral devices.


Top The Central Processor
The central processor (CPU) is the chip which acts as a control centre for all operations. It executes instructions (a program) which are contained in the memory section.

Basic operations involve

The CPU is said to be the brains of any computer system. It provides all the timing and control signals necessary to transfer data from one point to another in the system.


Top Programs: Instructions and Operand's
A program consists of a number of CPU instructions. Each instruction consists of

The instruction code specifies to the CPU what to do, where the data is located, and where the output data (if any) will be put.

Instructions are held in the memory section of the computer system. Instructions are transferred one at a time into the CPU, where they are decoded then executed. Instructions follow each other in successive memory locations.

Instructions
Fig 4_2: Program Instructions

Memory locations are numbered sequentially. The processor unit keeps track of the instruction it is executing by using a internal counter. This counter holds the location in memory of the instruction it is executing. Its name is the program counter (sometimes called instruction pointer).


Top Stored Program Control
Most computer systems today are stored program control systems. This means that the processor executes instructions which are stored in a memory subsystem. SPC systems are popular, because the processor does is simply changed by altering the instruction in the memory system. This makes for a general purpose computer system, capable of performing a wide variety of different tasks dependant upon the stored program contents.


Top Computer Memory
Memory contains data or instructions for the processor to execute. All memory has common features.


Top Types of Computer Memory
System memory consists of two main types.

  Advantages Disadvantages
Dynamic RAM Cheaper
Low Power
High Density
Slower
Needs refreshing
Static RAM Faster
No need to refresh
More Expensive
Consumes More Power
Low Density

Top Cache Memory
Cache memory is high speed memory which interfaces between the processor and the system memory. Dynamic memory is used to implement large memory systems in modern computers. This is due to features like low power consumption, high chip densities and low cost.

Cache memory
Fig 4_3: Cache Memory

Dynamic memory is however slow, and cannot keep up with modern fast processors. When a processor requests data from a memory chip, it expects to receive that data within a specific time. This is expressed as a number of clock cycles.

It is common for processors to run what is called a FOUR STAGE BUS CYCLE (which is four processor clocks long). Essentially, during the first processor clock cycle, the address is placed on the address bus. the second processor clock cycle is used to latch the address internally within the memory chip. The third processor clock cycle is used by the chip to find the data and place it on the data bus. The fourth processor clock cycle is used by the processor to latch the data on the data bus into its own internal hold register.

Dynamic memory is currently too slow to keep up with processors running at clock rates of 50MHz or greater (each cycle is 20ns). To use dynamic memory with fast processors requires extending the third processor clock cycle by another (or multiples thereof) processor clock cycle. The name for this extra processor clock cycle is called a wait state. What this does is change a four stage bus cycle into a five stage bus cycle (or greater), meaning that the fast processor is actually running just as fast as a slower processor (its being slowed down by the memory subsystem, whenever it accesses memory).

It is too expensive to use static memory in place of dynamic memory. To use slow dynamic memory with a fast processor requires an extra hardware subsystem (called cache memory) which fits between the processor and the memory subsystem.

All memory accesses by the processor are fed through the cache system. It comprises an address comparator which monitors the address requests by the processor, high speed static ram, and extra hardware chips.

The cache system starts off by trying to read as much data as possible from the dynamic memory subsystem. It stores this data in its own high speed static memory (or cache). When a processor request arrives, it checks to see if the address request is the same as that which it has already read from the memory sub-system. If it is, it supplies the data directly from its static cache. If the address is not cached, then it lets the processor access the main memory system directly (but the processor does this slower). The cache system then updates its own address counter it uses to read from system memory to that of the processors, and tries to read as much data as possible before the next processor request arrives.

When the cache system can respond to the processor request, its called a cache hit. If the cache system cannot service the processor request, its called a cache miss.


Top Input/Output Bus
The IO bus is the interconnection path between the processor and input/output devices (including memory). The bus is divided into THREE main sections

In more complex systems, the memory subsystem or peripheral devices also provide timing signals to complete data transfers, or initiate requests that the processor responds to (called interrupts).


Top Input/Output Peripheral Devices
Peripheral devices allow input and output to occur. Examples of peripheral devices are

The processor is involved in the initialisation and servicing of these peripheral devices.


Top Input/Output Processors
An input output processor is a special processor dedicated to handling peripheral devices like terminals, tape and disk units, and printers.

Mainframe systems like the IBM 370 use I/O processors to off load work from the system processor. This lets the system processor get more work done executing user programs without having to worry about handling data input and output to terminals or printing documents.

The PC has an I/O processor in the keyboard, which handles the complex operations of scanning the keys.

In addition, it is now becoming common to have I/O processors on graphics cards. The S3 graphics card is a good example of this, which supports hardware support for scrolling, sizing and moving windows. This removes these tasks from the system processor, and performs them at a much higher rate (up to 30 times faster).


Top IO CHANNEL COPROCESSOR (IBM)
To allow concurrent operation of the CPU and I/O devices requires the use of a special I/O processor. The main CPU instructs the I/O processor to perform the required data transfer. When the transfer is completed, the I/O processor informs the main processor of the status of the operation.

This method frees the main processor to perform other tasks whilst I/O is being done (tasks requesting I/O are blocked by the OS and thus not scheduled for processor time).

Typical features of an I/O channel processor system are

There are two main types of IO channels

Both channels support a number of devices on a bus called a sub-channel.

The selector channel operates in burst mode only. It handles a single sub-channel at a time, and has very high transfer rates. Typically, it controls high speed disk units.

The multiplexor channel handles more than one sub-channel at a time by interleaving requests. It operates in byte and word mode, but does support burst at a much lower rate than a selector channel. Typically, it handles devices like printers and character terminals.

Channel Operation
The processor initiates an I/O transfer by setting up a special IOC program in main memory. It then issues a STARTIO instruction, which identifies the channel and sub-channel.

The channel then accesses and runs the channel program (the address of which is in location 72). When finished, the channel updates the IO flag in the processors status register to signal command completion. The processor then checks the channel status register for results.

Each channel gets informed of

IBM Channel Operation
Fig 4_4: IBM Channel Operation


Top The Central Processor Revisited
We shall now take a closer look at how the processor functions internally.

The Fetch, Decode, Execute Cycle
Most modern processors work on the fetch, decode, execute principle. This is also called the Von Nuemen Architecture. The execution of an instruction by a processor is split into THREE distinct phases, Fetch, Decode, and Execute.

 

Graphical Animation of Instruction Fetch
The following graphic animation illustrates typical operation of an instruction by the processor. It places the contents of the instruction pointer onto the address bus and fetches the instruction. Once decoded, the instruction is executed and the instruction pointer altered to point to the next instruction.

Graphical animation of fetch cycle
Fig 4_8: Animation of Instruction Fetch


We shall now look at the internal operation of the CPU, and how it performs the fetch, decode, execute cycle. Internally, the CPU is made up of a number of discrete sections.


Top The Programming Model of a CPU
The programming model of a processor defines the registers within the processor which are visible and programmable by the user.

These include

Executing a program: An example
Lets consider the operation of the following program at the processor level.


	Assembler	High Level Language
	MOV AX, #1 	A := 1;
	MOV BX, #2 	B := 2;
	ADD AX, BX 	C := A + B;
	PUSH AX 	Writeln( C );
	CALL WRITELN

Assume that the instruction pointer contains the address of the first instruction.

  1. Place the address of the instruction (IP) on the address bus
  2. Read the value from that location into the instruction register.
  3. Decode the instruction (Mov AX, #1), increment the instruction pointer
  4. Read the operand from the next location and transfer it into the AX register
  5. Place the address of the instruction (IP) on the address bus
  6. Read the value from that location into the instruction register.
  7. Decode the instruction (Mov BX, #2), increment the instruction pointer
  8. Read the operand from the next location and transfer it into the BX register
  9. Place the address of the instruction (IP) on the address bus
  10. Read the value from that location into the instruction register.
  11. Decode the instruction (Add AX,BX), increment the instruction pointer
  12. Transfer BX to the ALU, and add with AX. Move the result back into AX
  13. Place the address of the instruction (IP) on the address bus
  14. Read the value from that location into the instruction register.
  15. Decode the instruction (Push AX), increment the instruction pointer
  16. Put the value of the stack pointer on the address bus
  17. Write the value of AX to that location
  18. Increment the stack pointer register value
  19. Place the address of the instruction (IP) on the address bus
  20. Read the value from that location into the instruction register.
  21. Decode the instruction (Call WRITELN), increment the instruction pointer
  22. Read the operands from the next two locations into an internal hold register
  23. Transfer the operands into the instruction pointer.

Top Base Units
The computer base unit houses the CPU, memory, floppy disk, hard disk drive, power supply unit, and peripheral cards which support printers and modems.

Computer Base Unit
Fig 4_9: Computer Base Unit

The expansion slots are used to plug in additional peripheral cards like sound cards, TV Tuners cards, video capture cards etc. The two main types of expansion slots are PCI and ISA.


Top Summary
Most modern Processors work on three cycles, fetch, decode and execute.

Processors use internal temporary storage areas for holding data, these are referred to as registers.

The set of registers which programmers can alter is referred to as the programming model.

The Arithmetic Logic Unit handles mathematical operations like add, subtract, multiply, divide, shift and rotate.


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Copyright Brian Brown, 1992-2000. All rights reserved.